COUPLED WITH ADVANCES IN TESTER ARCHITECTURES, DFCCT (DESIGN-FOR-CONCURRENT-CORE TEST) PROMISES TO KEEP TEST COSTS FROM OUTSTRIPPING THE MANUFAC- TURING COSTS OF COMPLEX SOCs

As device complexity grows and fabrication costs continue to fall, test is emerging as the largest expense in complex SOC (system-onchip) IC manufacturing. At the same time, ICs continue to exponentially increase in complexity, driving up test times. Many SOC devices incorporate multiple technologies, such as high-speed logic, DRAM, flash memory, and analog circuits. Testing these circuit types has historically required diverse types of ATE (automated test equipment). High-performance mixed-signal ATE is now available to handle SOC devices that contain multiple circuit types, eliminating the need for multiple test insertions. However, the multiple technologies’ different testing requirements normally require you to sequentially conduct tests, lengthening test times and raising manufacturing costs. IC manufacturers are looking for ways to significantly shorten test times and thereby reduce manufacturing costs. However, IC designers usually don’t consider the cost of testing. This situation is unfortunate, because eliminating a few seconds of test time would significantly reduce the cost of testing most SOCs.